Various types and configurations of non-volatile random access memory device have been developed, with a continued drive to minimize device size and maximize memory element density within the devices. Many emerging memory elements have a two-terminal structure and are configured as a 1-transistor-1-memory element (1T1M) cell. In the 1T1M cells, access transistor footprint generally dominates device size design constraints, with memory elements generally having significantly smaller dimensions than the access transistors. For example, various memory elements may have a footprint of about 4F2, where F represents Minimum Feature Size and is commonly employed as a unit of measure for memory elements. However, many access transistors have a footprint that is significantly higher than 4F2, with some access transistors having a footprint of up to 100F2 or larger due to transistor layout and current requirements.
Given the generally larger footprint of access transistors as compared to memory elements, memory device architecture has been developed to enable multiple memory elements to share a single access transistor. For example, crossbar arrays (CBAs) and shared access transistor designs have been proposed for increasing density of memory elements while maintaining the 1T1M cell configuration. With sharing of the single access transistor and shared electrical connections between memory elements, current leakage paths exist between the memory elements, with leakage current passing through non-selected memory elements. In particular, “current leakage”, as referred to herein, refers to loss of current through non-selected memory elements and bitline interconnections due to the interconnected relationship of the memory elements with selected memory elements and bitline connections. As a result, a signal for a selected memory element may be obscured due to the loss of leakage current through the other connected memory elements.
Accordingly, it is desirable to provide non-volatile random access memory device and methods of forming the same with maximized memory element density and with minimized current leakage between memory elements. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.